Logic Synthesis

Sintegra will take RTL and help create clocking architectures and apply constraints for timing and test, to synthesize the RTL into a gate-level netlist.  

 

During the process, Sintegra will map logic to process specific logic, insert test level logic verifying high test coverage, integrate IP, and verify that timing paths are valid and if not restructure the logic or help add waivers where needed.

Sintegra uses many techniques to optimize logic while making sure that the netlist is still equivalent to the RTL.  It is key now with low power to add in UPF specs into the RTL and to synthesize for lower power making sure the correct logic is in place to keep power where needed and to turn off power when not needed, and to protect devices.

Sintegra uses physical synthesis techniques to create a placement that is physically aware with power intent to make sure the design is compliant and meets all the design rules.  Design cycles today require a quick turn around but power aware SOC’s are even more critical than they have ever been.