Advanced Clock Structures

Low power is a large concern as we move more towards mobile platforms.  Power management is key in this area and many SOC’s now have Power Management Controllers on the SOC.  These can gate clocking to shut down power consumption on the chip.  

 

At Sintegra we are knowledgeable on many methods to help with clocking a SOC to save on power and meet timing.  Some of those include:

• ICG (Integrated Clock Gating) cells and their placement and driving capabilities

• Early clocking devices to help in timing

• Mixing test clocks and regular clocks and how to not increase hold buffering

• Decreasing clock latency

• Optimizing transition times for best timing results while not consuming too much power

• Clock spreading to reduce the current load in power switchers

• Spacing rules to decrease noise to and from the clock signals

• Upper layer assignment to increase the speed of the clock