Sintegra understands the push for low power.  Having worked with some of the most advanced processes in the world and design styles the portfolio of designs we have worked with is extensive.  More capabilities for the SOC usually means more power, but the expectation is less power with more features.  There are many techniques to help reduce power and here are few of the many we have experience in:

  • Clock gating (Integrated Clock Gating cells at synthesis)

  • Multi-Vt libraries

  • Voltage Areas

  • Power Switches

  • Level Shifters

  • Feed thru cells (self isolation)

  • IP with built in switching

  • Power planning between VA

  • Optimal stand cell switching