Full Chip Planning

Sintegra is capable of handling all your full chip planning.  If you are channel based or abutted we understand the complexity each brings and how to create a design that is robust and efficient.  Working with different types of packing technology and the best layout for the design based on packaging and functionality of your design.  Placement and pin assignment are done full chip when able to ensuring proper pin placement and pushdown or macros and IP blocks.  In the case of an abutted design feedthrus are created and are minimized to reduce impact to lower level blocks.  Clock tree structures must be planned out as well and all of this takes place while being low power aware for voltage areas that may shut down.